The proliferation of VLSI (very large scale integration) chips for the miniaturization of complex electronic equipment has brought about new kinds of problems which tend to defeat the advantages of VLSI technology. Among others, these problems include: (1) the large number of terminals associated with VLSI chips produces complex, expensive circuit board layouts and long interconnection lines which in turn cause skew problems and require high power consuming, heat-generating drivers; (2) a failure in any part of the chip usually makes the whole chip inoperative; and (3) the vast number of specialized chips available on the market results in uneconomical short runs and makes it difficult for designers to keep up with what the market has to offer.
Prior art in this field includes U.S. Pat. No. 3,611,317 which deals with printed circuit board layouts but does not teach elimination of long IC interconnections nor a universal board configuration; U.S. Pat. No. 4,107,760 which shows a flat peripheral heat sink for a circuit board which does not encounter the thermal expansion compensation problems solved by this invention; U.S. Pat. No. 4,246,597 which shows an add-on device for cooling a multi-chip module; U.S. Pat. No. 4,296,456 which deals with a high-bandwidth IC package but does not show the leadless I/O serial data connection scheme of this invention; U.S. Pat. No. 4,398,208 which deals with an IC package that uses a multilayer substrate but does not have the leadless interconnection feature of this invention; U.S Pat. No. 4,437,141 which deals with outside-world connections for large terminal count IC chips; U.S. Pat. No. 4,484,215 which deals with a flexible mounting support for immersion cooling of wafer scale IC's; U.S. Pat. No. 4,489,363 which deals with a cooling method not suited to high density IC packaging; U.S. Pat. No. 4,549,200 which deals with a multi-level modular approach not suited to the leadless packaging of this invention; U.S. Pat. No. 4,551,746 which relates to a stacked chip array; and U.S. Pat. No. 4,578,697 which deals with a packaging method using printed-circuit-type interconnections.